17+ years of experience working in Mixed Signal ASIC design and Digital SOC design. Involved in everything IC, with design/verification of both analog/digital blocks, as well as system level debug. Extensive Hardware and Software experience with B. tech and MS degrees in Electrical engineering, Computer Science and Computer Engineering.
Education:
Purdue University, West Lafayette, IN: Master of Science in electrical and Computer Engineering in 2003. Major in Computer Engineering, Minor in VLSI/circuit design.
- Research Assistant in ECE & CS for 2 years (Advisors: Dr. T. N. Vijaykumar in ECE and Dr. Tony Hosking in CS), working on “Architectural support for Garbage collection for Object Oriented languages”.
- Projects in: Computer Architecture, Compilers, Operating systems, Cryptography, Internetworking, Parallel Computer Systems, IC Fabrication.
Indian Institute of Technology (IIT), Kanpur, India: Bachelor of Technology in Electrical Engineering in 2001. Major in Electrical Engineering, Minor in Computer Science and Engineering.
- Projects in: VLSI design, Motors, Power electronics, Data Structures/Algorithms, Database Management.
Experience:
My experience is both in analog and digital design as well as verification. Analog design involves designing comparators, op-amps, bandgap, sram, etc, while digitsl design experience involves taking a design from RTL to GDS.
Worked at Advanced Micro Devices (AMD) 2003-2011.
- Involved in designing custom digital logic and memory circuits for x86 processors from 130nm to 28nm process in both bulk and SOI technology.
- Involved in Platform level Silicon Debug requiring extensive x86 knowledge at the system level.
Worked at Texas Instruments (TI) 2011-2018.
- Involved in digital and analog design and verification of Mixed Signal ICs in 350nm to 65nm process in bulk technology. ASICs designed for Touchscreen Controller, Printers, PMIC, Battery Management, Disk Drives, Motor Drivers, Smoke detector, Security IC and anything else that makes at least few cents of profit.
- Involved in System level debug and silicon validation of these ICs requiring extensive cross disciplinary interaction.
Working at Apple Inc (APPLE) 2018-present.
- Involved in design of various SOC chips used across various Apple products in sub 10nm process in FinFet Technology.
- Responsible for taking design from RTL to GDS running state of the art industry cad tools on Multi Billion transistor design.
Other Achievements:
- Awarded NTSE Scholarship by NCERT, Govt. of India for entire study. (750 selected from all of India)
- Secured 7th rank in Bihar State Maths Olympiad by NBHM, Govt. of India. (500 selected from all of India). Scored 24/100 in National Maths Olympiad (top 30 selection from India at 33/100).
- Competent Toatmaster (CTM) and Competent Leader (CL) awards from ToastMasters Club.
- Blue Belt II in Taekwondo Martial arts.
